Design techniques for secure cryptographic circuits in deep submicron technologies

In accordance to the discussion done in Chapter 2, and in particular with reference to Fig. 2.4, a TEL circuit can be implemented both using standard-cell logic gates and full custom cells. For this purpose, we have chosen this second option, which allows to better exploit the performances of the TEL circuit because relies on a transistor-level optimization. Furthermore, a full custom solution can be directly tested using SPICE simulations, in order to make the logic style prone for being implemented on a cryptographic ASIC, which represents the final scope of our work.

The first step in the design of a TEL implementation has been the study of the digital logic styles presented in literature with the aim of counteracting PAAs. For this purpose, we have identified two full custom logic styles as reference from which this work is started: the Three-phase Dual-rail Precharge Logic (TDPL) [21] and the Delay-based Dual-rail Precharge Logic (DDPL) [20], which have been both implemented in our department in last years.

Basically, TDPL is an improvement of the SABL style, enhanced with the presence of an additional output transistor in the circuit scheme of the logic cells, which introduces a third state in the logic data encoding, the postcharge, with the purpose of balancing the energy of the gate in presence of capacitance mismatches. TDPL circuit requires the routing of a second clock signal, which represents the control signal ctrl in Fig. 2.7. However, this poses a constraint on the layout of the circuit, because routing an additional dynamic signal requires to enlarge the design in order to avoid the effect of cross-coupling which may introduce crosstalk and impact the functionality of the circuit; moreover, the relevant interval of the data encoding is still too large, due to the presence of the sense amplifier.

On the contrary, the DDPL style is an improvement of TDPL, and is based on the following observation: to obtain the same result of the TDPL, that is balancing the energy of the circuit even in presence of unbalanced capacitances, it is possible to reduce the redundancy of the time interval length: instead of encoding a bit in a relevant interval fixed by the clock period, it is possible to generate a differential signal pair where the relevant time is reduced down to, which represents a fraction of the clock period. This way, it is possible on a side to improve the energy balancing activity of the circuit also if two differential output capacitances are mismatched by reducing as much as possible, and at the same time this can be done irrespective of the clock frequency.