Cache-Simulator of a MultiProcessor Architecture for AXE CP

4 INTRODUCTION This work has been developed within Ericsson UAB, commissioned by a project named Multi-X whose task is the evaluation of techniques for speculative execution of existing applications on a symmetric multiprocessor platform. Among the factors that affect the performances of such a system, mainly together with rollback frequency and job distribution, there is the cache behaviour, because it directly influences the bus traffic. What is fundamental to understand is that true cache statistics are highly dependent upon the exact target system, both hardware and software, and there is no substitution for determining the characteristics of a certain system. Therefore, results given by the many previous works on this field cannot be considered reliable enough. In order to predict if and how our memory system is a bottleneck, the most common procedure in a design phase is the construction of a simulator. The simulator is made to emulate different sorts of caches, and the model is made to run software applications that will be run on the target system. Two are the main goals for our program: 1. Given a cache system and the applications, to estimate the traffic on the bus and to suggest possible ways of improvement 2. Given the applications, to find the cache system that fits the best For doing that, it has to be able to work with a variety of configurations and policies; of course the highest priority has been given to those that are already implemented in real systems. In the development we followed an object-oriented approach, making easier further modifications and features additions. The changeable parameters are the cache structure, how many levels and if data and instructions are to be treated separately, the cache size, the block size, the associativity and the policies: the cache coherence protocol and the replacement algorithm. As said before the considered system is symmetric: the main memory is uniformly accessed by all the processors; nevertheless each processor has its own cache system, which can be different from the others’ one. The simulator is trace-driven, that means it gets as input a file with memory references recorded from a fairly similar system. In our case, it is a multiprocessor running traffic for a telecommunication environment; however the simulator is not designed to target just the telecom servers but rather to be a general cache simulation system. The output is a collection of statistics, for instance the percentage of cache hits and misses. Reads and writes, data and instructions, and different levels are analysed separately, because they can involve different behaviours. Moreover in case of bus accesses, we distinguish the possible causes. In this way we are able to individuate the trade-offs between the different configurations and policies. The work and the report itself consist of two stages: the first is described by Part 1 of this document, and it is a literature survey of available techniques for implementation of cache models and cache coherence protocols in SMP. The different performance evaluation methodologies are presented, together with an explanation of the results and the applications we aim to measure. Some of the related works are also cited, emphasising the differences with ours. Part 2 deals with the design and the implementation of the simulator. Because of the object-oriented approach, suitable documentation is provided, mostly in UML that is the standard modelling language. The programming language instead is C++. Finally, at the end of the report, the reader can find four appendices, useful during the reading of the previous chapters (as the glossary in Appendix D) or during the execution of the program (as the user manual in Appendix A). For further maintenance, the description of the data structures and the commented listings can be found in Appendix B and C.