Design techniques for secure cryptographic circuits in deep submicron technologies

One of the main concerns of modern cryptographic devices is related to the possibility of stealing the secret information, which is processed or stored inside (e.g. personal data, PIN, passwords, payment details, ...). In the scientific community many efforts have been spent in the last decades, with the purpose to develop cryptographic algorithms, which are robust enough against any attempt to detect the cryptographic key of the algorithm itself. In the last years a new class of attacks, aimed at attacking one device at the physical level, gained even more importance. Their efficacy consists in the possibility to exploit the physical emissions of the device (e.g. power consumption, light, noise, electromagnetic radiation, ...), instead that trying to break the algorithm from a mathematical point of view. This class of attacks is known as Side Channel Attacks (SCAs) and their danger resides in the fact that they allow to steal the information leaking from the device, without leaving any trace of their activity, so that the victim of the attack (e.g. the owner of a smart card) could be completely unaware of them. Many countermeasures have been presented at each design level, in order to protect electronic circuits, which are the hardware basis of any cryptographic device, against them. In this work we focus on a particular class of SCAs: Power Analysis Attacks (PAAs). PAAs are able to find correlation between the power consumption of a digital circuit and the electrically internally processed data, exploiting the fact that with the reduction of the dimensions of the commercial electronic technologies this dependance becomes even more relevant. Therefore the new challenge of the semiconductor companies is to design and manufacture devices which are proven against this class of attacks, already from a hardware point of view, in order to provide the customer with reliable and optimized products.
The main contributions of this work are below summarized:
- Present a new concept for the design of digital cryptographic circuits, whose purpose is to increase the level of securiy of crypto-devices against hardware attacks, in particulat against PAAs.
- Discuss the most known state-of-the-art security metrics and present a new methodology, as an improvement of the former ones, which should be considered in order to properly validate sub-micron cryptographic circuits.
- Design a new digital standard cell library, using a commercial sub-micron technology node, which has been characterized with extensive simulations using commercial EDA tools and has been evaluated using the most common security metrics.
- Define a new design flow, using the proposed standard cell library, which has been adopted for the design of a cryptographic test-chip; the design phases and the security evaluation of the test-chip are widely described and allow to prove the level of robustness of the new design style.
- Discuss a new class of Power Analysis Attacks, based on the leakage coming from the static power, which is becoming predominant in scaled sub-micron technologies, and prove through extensive simulations that the most known countermeasures against PAAs are not robust enough and therefore new metrics and design styles would be necessary.