Abstract
i
Abstract
The operational transconductance amplifier (OTA) is a core building block in most
analog and mixed-signal electronic systems. Due to the increasingly demand of
high-gain, large-bandwidth and wide-swing amplifiers, capable of driving large
capacitive loads under low-voltage and low-power conditions, in recent years many
researchers have proposed several compensation topologies for three-stage
amplifiers. Indeed, a three-stage amplifier represents the only viable option the
achieve DC gains in excess of 100dB in a low-voltage low-power environment,
especially when deep sub-micron CMOS technologies are adopted.
Unfortunately, an effective design procedure based on closed-form equations
involving the principal performance parameters is still missing. Besides, the
compensation network design is usually carried out by neglecting the effect of
zeroes and assuming a Butterworth unity-feedback frequency response. As a result,
the designer cannot set the compensation network for the desired phase margin, as
usually done in two-stage amplifiers.
Despite the transfer function complexity, which often made it difficult to derive
stability conditions of reasonable practicality, this work provides a systematic design
procedure exploiting the phase margin as main design parameter.
Abstract
ii
The present dissertation provides an overview and study on frequency
compensation techniques for three-stage amplifiers and develops several novel
techniques. The work is divided into two main parts.
In the first part the existing solutions are reviewed and discussed by developing a
design-oriented methodology which exploits the phase margin as main design
parameter. Besides discussing the mathematical basis of all the considered
compensation methods, the dissertation supplies a strong theoretical analysis along
with many transistor-level simulation examples to support the adopted compensation
criteria. Furthermore, an analytical performance comparison was developed
allowing a better understanding of the real benefits of a specific compensation
strategy, irrespectively of the particular technology and topology used to implement
the amplifier.
The second part of the dissertation proposes several original compensation
topologies for three-stage amplifiers which are the direct result of a systematic
research study. The differences as well as the advantages and drawbacks of each
topology have been carefully investigated. Many of these solutions were exploited to
fabricate several OTAs which were experimentally tested. A performance
comparison with previously reported solutions showed a significant improvement of
the proposed compensation topologies in terms of small-signal and large-signal
performances.
CHAPTER 1 Introduction
1
CHAPTER 1
Introduction
As predicted by G. Moore [1], [2], the exponential reduction of MOS transistor
feature size has enabled fast and reliable digital processing [3]. To ensure sufficient
lifetime for digital circuitry and to keep power consumption at an acceptable level,
the dimension-shrink is accompanied by lowering of nominal supply voltages [4].
While technology scaling is always desirable for digital circuits due to reduced
power, area and delay, it is not necessarily helpful for analog circuits since dealing
with precision requirements or signals from a fixed voltage range is more difficult
with scaled supply voltages [1]-[3], [5]-[7].
Most of today’s ICs are of the type system-on-a-chip (SOC) which contain,
besides a typically large digital core, several analog building blocks. From the
integration point of view, the analog electronics would ideally be realized on the
same die and consequently must cope with the CMOS evolution dictated by the
digital circuit. In particular, the reduction of supply voltages represents a serious
challenge for analog designers, because the signal headroom becomes too small to
design circuit with sufficient signal integrity at reasonable power consumption
CHAPTER 1 Introduction
2
levels. Furthermore, analog circuits cannot be designed using minimum size devices,
for reasons of gain, offset, noise, etc. [7]-[9]. As a consequence, the chip area of the
analog part cannot be drastically reduced with the lowered feature size and power
supply.
Primary among key analog signal-processing blocks is the operational
transconductance amplifier (OTA). High gain amplifiers are required in a variety of
applications, including highly linear continuous time filters, high-accuracy pipeline
analog-to-digital converters, high-linearity capacitive/resistive DSL line drivers,
high-Q switched capacitor filters, etc. [10]-[13]. In the past high-gain OTAs have
been realized by cascoding devices to generate high-output impedances. Since the
threshold voltage does not scale down proportionally to transistor dimensions [3],
[14], cascoding with power supply voltages lower than 3 V leads to unfeasible
voltage swings. Presently, amplifiers exhibiting a DC gain in excess of 100 dB can
be profitably implemented by cascading three transconductance gain stages.
However, this approach poses major difficulties in frequency compensation as the
increased number of high impedance nodes (and, in turn, of low frequency poles)
may result in instability.
In order to keep pace with contemporary developments in digital circuit design,
the realization of high-performance compact low-voltage and low-power operational
amplifiers continues to challenge analog designers. The impelling urge to match the
high level of accuracy and dynamic range of modern digital processing is one of the
most challenging design issue for next generations’ analog circuit design.
CHAPTER 1 Introduction
3
1.1 Scaling impact on analog performance
For most of today’s mixed-signal designs - and particularly in classical analog
design - the processed signal is represented by a voltage difference, so that the
supply voltage determines the maximum signal. Decreasing supplies, as
consequence of constant-field scaling, means decreasing the maximum achievable
signal level. This has a strong impact on mixed-signal product development for SOC
solutions. Typical development time for new mixed-signal parts is much longer than
for digital and memory parts; sheer lack of design resources thus becomes another
key challenge. An ideal design process would reuse existing mixed-signal designs
and adjust parameters to meet interface specifications between a given SOC and the
outside world, but such reuse depends on a second type of MOSFET that does not
scale its maximum operating voltage [3].
Although the analog transistor properties do not really get worse when comparing
them at identical bias conditions, lower supply voltages require biasing at lower
operating voltages which results in worse transistor properties, and hence yield
circuits with lower performance [7], [14].
Fig. 1.1 shows the power increase of a unity-gain voltage buffer with fixed
topology and performance implemented using different technologies [7]. It is
apparent that for a given power budget the performance drops when migrating to
newer technologies.
Let us briefly better explain the results of Fig. 1.1 from a quantitative point of
view. Assume that we want to maintain constant both the dynamic range and the
bandwidth of a generic voltage amplifier driving a capacitive load C. Denoting with
CHAPTER 1 Introduction
4
V the signal amplitude at the output of the circuit, the dynamic range, evaluated only
considering the thermal noise over the total noise bandwidth of the circuit, is
expressed as
n
V V
DNR
v
kT C
(1.1)
where kT are Boltzmann’s constant and the temperature, respectively, and the gain-
bandwidth product, as a general rule, is given by
m
g
GBW
C
(1.2)
where g
m
represents the transconductance of the amplifier (or the transconductance
of one of its stages, if a multistage amplifier is used). If the power supply voltage is
reduced by the scaling factor , since we can infer that also the signal amplitude is
reduced by the same factor to accommodate gate-source overdrive voltage and
saturation. Consequently, to maintain constant the DNR we must increase C by
2
from (1.1). At the same time, to maintain constant the GBW, g
m
must be increased
by
2
as well. Therefore, an additional power dissipation (and/or area occupation) is
required to maintain performance when lower supply voltages are used.
Furthermore, the matching properties are more dominant in determining the low-end
of the dynamic range than noise in some systems, such as in ADC front end circuitry
CHAPTER 1 Introduction
5
[15]. Since matching is reported to scale down with oxide thickness [3] and the
power constraints due to matching are several orders of magnitude higher than for
thermal noise [9], the power penalty due to the use of a newer technology is much
more noticeable in these cases and becomes a serious problem in sub-90-nm
technologies, where for large area (long) transistors mismatch will be dominated by
gate leakage mismatch which puts a new upper limit on achievable matching
performance. Increasing area does not automatically improve matching anymore
except if increased power consumption is accepted (or by using active cancellation
techniques) [7]. It follows that long transistors cannot be usefully applied anymore
in ultra deep submicron technologies.
Another important issue regards the transistor voltage gain. Figure 1.2 shows the
transistor voltage gain, following from nonlinearly interpolated measurements,
under the assumption that the quiescent V
DS
and the signal swing are decreased
proportionally to the nominal supply voltage at a constant transistor length [7]. A
significant reduction in transistor voltage gain is observed for scaled processes. With
this scaling scenario, higher harmonic components may increase in amplitude
despite the smaller signal level.
The voltage gain degradation can only be compensated at circuit level by gain-
boosting techniques [16], [17]. These, however, are harder to fit within decreasing
supply voltages, since they require cascoding. Indeed, a cascode amplifier presents a
swing loss of about 2V
GS
+ V
DS
which critically affects the maximum achievable
range of signal amplification [10]-[13]. Low threshold voltages CMOS technologies
may be used to mitigate the voltage swing limitations, but economic and
CHAPTER 1 Introduction
6
performance concerns persist regarding production control of the low-V
t
values and
associated leakage currents [3]. In conclusion, the only viable option to achieve high
DC gains in a low voltage environment is represented by multistage amplifiers.
Fig. 1.1 – Minimum power consumption for an (arbitrary) analog circuit with fixed topology and
performance as a function of the supply voltage, for four technologies. Pushpins correspond to the
power consumption in a technology at the nominal supply voltage for each CMOS process [7].
Fig. 1.2 – Gain of transistors as a function of the gate-overdrive voltage with V
DS
proportional to
the nominal supply voltage (0.3 V for 250 nm) and L = 1 m for four technologies.
CHAPTER 1 Introduction
7
1.2 Multistage amplifiers
Due to output impedance degradation and reduced supply voltages, multistage
amplifiers becomes the only alternative to achieve an adequate high gain in low
power environments, especially when sub-micron technologies are adopted [18]-
[22].
Among the advantages of multistage amplifiers, the excellent harmonic distortion
performance is a peculiar characteristic of these circuits [17], [20]-[21]. Indeed, each
negative feedback loop around the output devices reduces the open loop THD by
each loop’s gain.
However, multistage amplifiers pose several design challenges. Indeed, compared
to a cascode single stage amplifier, the complexity of the circuitry (and power
consumption) is increased and, what is more, some stages inevitably contribute
poles that lie within the unity-gain bandwidth which may lead to instability.
Presently, a good compromise between circuit complexity, power dissipation and a
sufficiently high DC gain (in excess of 100 dB) is represented by three-stage
amplifiers [23]-[47].
Unfortunately, the increased number of low frequency poles may seriously
compromise closed-loop stability. Hence, the devise of a suitable compensation
network is one of the most challenging task in the design of a three-stage amplifier.
Compensation of a three stage amplifier, where the second stage is non-inverting
and the last is inverting, is obtained through the Nested Miller Compensation
(NMC) technique shown in Fig. 1.3 [18]-[24]. This approach employs two
compensation capacitors which exploit the Miller effect to split the low frequency
CHAPTER 1 Introduction
8
poles and achieve the desired phase margin and transient response. However, this
solution results in bandwidth and slew rate reduction (the gain-bandwidth product is
one-quarter as that achievable by a single stage amplifier, [30]) and in a high power
consumption. Recently, different compensation topologies have been proposed in
order to overcome the inherent limits of NMC [25]-[40].
When the inner OTA stage is the only inverting one, another kind of compensation
scheme, termed the Reversed Nested Miller Compensation (RNMC) is the most
suitable option [23]-[24], [41]-[45]. This technique exploits the same operating
principle of the NMC but provides an inherent bandwidth improvement since, as
shown in Fig. 1.4, the inner compensation capacitor does not load the output node
[4], [19]. Many researchers have recently proposed several improvements of the
basic RNMC compensation topology [41]-[45].
g m 2
g
m 3
+
-
A
v2
A
v3
+
g
m 1
A
v1
C L
C
C1
C C2
V in
V out
Fig. 1.3 – Block diagram of the basic NMC.
CHAPTER 1 Introduction
9
g m2
g m3
-
+
A v2
A v3
+
g m1
A v1
C L
C
C1
C C2
V in
V
out
Fig. 1.4 – Block diagram of the basic RNMC.
1.3 Structure of the thesis
The aim of this work is to analyze the three-stage amplifiers state of the art and to
improve the topologies proposed in the literature by designing high performance
three-stage amplifiers based on the NMC and RNMC.
The thesis is organized as follows. In chapter 2 some of the most common
frequency compensation techniques for three-stage operational transconductance
amplifiers, with the last stage inverting, will be compared by introducing an
analytical figure of merit. In particular, design equations adopting the phase margin
as an explicit design variable will be carried out. It is shown that there is no unique
optimal solution as this depends on the load condition and the relative magnitude of
the transconductance of each stage. From this point of view, the proposed
comparison also provides useful design guidelines for the optimization of the small-
signal performance.
CHAPTER 1 Introduction
10
In Chapter 3 some novel compensation topologies improving the basic NMC and
RNMC techniques will be developed. Design equations introducing the phase
margin as main design parameter will be carried out. Moreover, some of the
proposed techniques will be implemented and experimentally tested. A performance
comparison between the proposed solutions and those previously reported in
literature is carried out, showing a significant improvement in both small signal and
large signal performances of the amplifiers designed, especially those based on the
RNMC topology.
Chapter 4 points out the main achievements of this work and the future
perspectives.
In Appendix A a Matlab tool for the symbolic analysis of linear analog circuits
called SALCIM (Symbolic Analysis of Linear CIrcuits in Matlab) is presented. The
tool was extensively used throughout the thesis to symbolically solve and carry out
the open-loop transfer function of the various three-stage amplifier topologies,
which is the first step for the design of the compensation network.
In Appendix B design procedures for three-stage CMOS OTAs employing nested-
Miller frequency compensation are presented. The approaches developed are simple
as they do not introduce unnecessary circuit constraints and yield accurate results.
They are hence suited for a pencil-and-paper design, but can be easily integrated into
an analog knowledge-based CAD tool.
Finally, Appendix C presents some useful results for a generic three-stage
amplifier are developed.
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