Failure Analysis for System in Package devices using Magnetic Microscopy

CHAPTER 1. INTRODUCTION 2
To avoid these situations, industry follow quality and feasibility proce-
dures. Failure analysis intervenes as much as possible in the fabrication chain,
since the cost of a failure follows the rule showed in table (1.1).
Fault found at: Cost of die:
Chip level X
Board level 10X
System level 100X
Table 1.1: Rule of ten
1.1 The Author’s Work
The author has been working on a Failure Analysis project at the Centre
National d’Etudes Spatiales (CNES) of Toulouse, France.
As new technologies in the electronic environment develop from 2D In-
tegrated Circuits to 3D complex packages, it becomes necessary to find new
techniques to detect and localize the different kinds of failures. The project
carried out by the author, led by Dr. Philippe Perdu, is aimed to find a so-
lution to localize defects for System in Package (SiP) devices. This is done
by measuring the magnetic field, which is generated by the current flowing
through the device, with a Magnetic Microscope (Magma C20) and compar-
ing it with several simulated faults in order to choose the most probable one.
In Chapter 2 there is a short description of the work environment, speci-
fying the general purpose of CNES and the Expertise Laboratory work which
is where this project evolved.
In Chapter 3 the Failure Analysis problem is discussed and a short de-
scription of the existing techniques is given.
CHAPTER 1. INTRODUCTION 3
To fully understand the new developed technique, in Chapter 4 and Chap-
ter 5, firstly, how static currents generate a magnetic field is described (Biot-
Savart Law). Following this, how to find the current distribution analytically
once given the map of the magnetic field is shown.
In Chapter 6 the author’s work on the evaluation of three different simu-
lation software is described together with some background theory on Finite
Element Analysis.
For the hardware tool used to map the magnetic field, a SQUID device
was chosen after comparing several magnetic sensors, as described in Chapter
7.
Chapter 8 describes how a sample was designed and manufactured, and
how different simulations of it were done.
In Chapter 9 the tool used to take the measurements and the measure-
ments taken are described.
Finally in Chapter 10 the correlation between the simulation and the
measurements was calculated to validate the new technique.
Chapter 2
Work Environment
2.1 CNES
Founded in 1961, the Centre National d’Etudes Spatiales (CNES) is the
government agency responsible for shaping and implementing France’s space
policy in Europe.
Its task is to invent the space systems of the future, bring space technolo-
gies to maturity and guarantee France’s independent access to space. CNES
is a pivotal player in Europe’s space program, and a major source of initia-
tives and proposals that aim to maintain France and Europe’s competitive
edge.
It conceives and executes space programs with its partners in the scien-
tific community and industry, and is closely involved in many international
cooperation programs.
The agency’s more-than 2,400-strong workforce constitutes an exceptional
pool of talent, with some 1,800 engineers and executives.
The CNES headquarters is in Paris. The transportation division (DLA),
which is in charge of space development-related missions, is located in Evry.
Space programs and research and development of operation systems are car-
4
CHAPTER 2. WORK ENVIRONMENT 5
ried out at the Toulouse Space Center. CNES also has the Guyana Space
Center (CSG) in French Guyana, with a rocket launch site and test facility.
Through its ability to innovate and its forward-looking vision, CNES
is helping to foster new technologies that will benefit society as a whole,
focusing on:
ˆ Access to space
ˆ Civil applications of space
ˆ Sustainable development
ˆ Science and technology research
ˆ Security and defense
Figure 2.1: CNES Toulouse center
2.2 Central Laboratory for Expertise
The Central Laboratory for Expertise in Electronics, Mechanisms, Materials
and Contamination performs technical analysis in the following domains:
CHAPTER 2. WORK ENVIRONMENT 6
ˆ Electronics: EEE components and microelectronics technologies
ˆ Mechanisms and materials
ˆ Micro and nanotechnologies
ˆ Contamination
Technical expert assessments are made in the frame of space projects to
support R&T (Research & Technology) activities.
In the electronics field, the Central Laboratory contributes to the eval-
uation of EEE (Electrical, Electronic and Electromechanical) components
(including radiation evaluation) thanks to state-of-the-art equipment in elec-
trical characterization and failure localization for advanced VLSI.
In the mechanisms/material domain, failure analyses are performed for
all types of materials (composite, polymer, metallic, ceramic), using con-
ventional means as well as advanced specific tools such as nanoindentor or
AFM.
Spectral characterization, chemical function or molecular analysis of con-
taminants can be performed by various analytical chemistry techniques, which
can be coupled with environmental facilities.
The Central Laboratory plays a leading role in the development of micro
and nanotechnologies especially in terms of characterization and reliability
aspects.
2.2.1 Technological analysis/Failure analysis
Evaluation of state-of-the-art technology is performed through technological
analysis.
Failure analysis techniques are used to confirm and localize physical de-
fects. The final objetive is to find the root cause.
CHAPTER 2. WORK ENVIRONMENT 7
2.2.2 MEMS Mechanical Characterization
Controlled loads, applied to the sample thanks to a diamond tip positioned
with precision through nanopositioning, make it possible to conduct a 3D
scan of the surface of the MEMS.
2.2.3 Electrical Characterization
Electrical characterization is generally the first step in the failure analysis
process of EEE components. However, the CNES characterization platform
is widely used for upgrading and specification verification during endurance
and radiation tests.
2.2.4 Mechanical Characterization
Mechanical tests are performed by the laboratory (tensile, compressive and
bending tests) on any kind of material. Additional thermal chambers allow
characterizations in the −100C° to 300C° temperature range.
2.2.5 FIB Farm
FIB (Focused Ion Beam) is a tool used for design modification and in situ
cross-sectioning. The laboratory FIB equipment (FIB Farm) can be used on
last generation circuits for modification (front and back side, including copper
capability) and cross-sectioning (dual beam capability, micromanipulation for
MEMS analysis and nanoanalysis).
2.2.6 Reliability testing
Reliability tests are used to eliminate newly emerging problems and assess
product strength and operational life expectancy.
CHAPTER 2. WORK ENVIRONMENT 8
2.2.7 Thermal Analysis
The testing machines are used to perform characterization in the −150C°
to 500C° temperature range. Glass transition temperature measurement is
performed with a Differential Scanning Calorimeter for viscosity and elastic
modulus.
2.2.8 Contamination
Different analysis for organic contaminants are possible using various equip-
ment in the laboratory. Different analytical chemistry techniques are used:
ˆ Spectrophotometry
ˆ Residual gas analysis
ˆ Thermal analysis
Chapter 3
Failure Analysis techniques
The main aim of Failure Analysis is to determine the root cause of the fault.
This is done by using different tests: it is in fact fundamental to find out if
the problem is due to irregular use of the device or to an internal defect [26].
3.1 Process Flow
It is possible to define three different stages of the analysis:
ˆ Electrical diagnosis
ˆ Fault localization
ˆ Physic-Chemical analysis
3.1.1 Electrical diagnosis
This stage is necessary to pre-localize the defects. To obtain the diagnosis,
several techniques, which are often complementary, are used.
The electrical diagnostic process usually involves measuring the current
in relation to the voltage, analysis of the test vectors, measuring the con-
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CHAPTER 3. FAILURE ANALYSIS TECHNIQUES 10
sumption of the test vectors and then calculating the difference between the
expected signals and those measured.
The electrical analysis provides the first indication of the origin of the
defect and facilitates the choice of the most suitable method of localization.
3.1.2 Fault localization
In order to localize the failure, two types of analysis can be used: Non De-
structive Evaluation (NDE) and destructive evaluation.
NDE is used to provide information on the localization, mechanism and
cause of the failure without causing damage to the circuit, so that it remains
operational.
The preparation of the circuit can go from simply opening the package
to its complete passivation giving access to the metal tracks. It should be
noted that in the case of RF circuits, a circuit in an open package will not
behave in the same way as one in a closed package, which imposes additional
constraints on the choice of the method of analysis.
For the purpose of failure localization, several techniques, which are of-
ten complementary, are used: Magnetic Field Cartography, analysis of test
vectors, measurement of the consumption of the test vectors, shmoo plot or
analysis of the electrical signatures.
3.1.3 Physic-Chemical analysis
Once the failure has been localized, the next step is to use destructive prepa-
rations of the sample in order to reveal the internal structure of the circuit.
These analyses are often necessary to check the mechanisms and the causes
of the failures and to be able to correct them.
CHAPTER 3. FAILURE ANALYSIS TECHNIQUES 11
3.2 Failures at Integrated Circuit level
Inside an Integrated Circuit several different kinds of failures can occur. It is
of fundamental importance to study and understand them so that they can
be avoided during the manufacturing process.
3.2.1 The electromigration phenomenon
In an integrated circuit, the presence of a high current density can produce
a great transfer of energy between the electrons and the atoms of the metal
tracks. The physical consequences of this phenomenon are:
ˆ The creation of holes in metalizations causing an increase of the resis-
tivity of the lines which is high enough to act as an open circuit.
ˆ An increase of the mechanical constraints in the dielectric could cause
a break in the dielectric itself and create short circuits between close
interconnections [10].
As circuit density continues to increase and line widths continue to shrink,
interconnections are increasingly important in defining not only the perfor-
mance of the device, but also its overall reliability. Electromigration, which
results from the moment exchange between current carrying electrons and
the host metal lattice, may produce voids in the metalization or increased
stress in the supporting dielectrics.
Voids will result in increased line resistance or even in open circuits, while
increased mechanical stress may result in dielectric fractures and leakage
between adjacent interconnections.
The rate of the electromigration is primarily dependent upon the current
density and line temperature following the generally accepted Black model:
TF = A0(J − Jcrit)−N · e
Ea
kT (3.1)
CHAPTER 3. FAILURE ANALYSIS TECHNIQUES 12
Figure 3.1: A crack in a line
where:
TF = Time to Failure
A0 = Constant related to the material and process conditions
J = Current density
Jcrit = Critical (threshold) current density necessary to produce failure
Ea = Thermal activation energy
K = Boltzmann constant
T = Line temperature
Generally, both the average current density (J) and average temperature
(T ) increase as semiconductor technology develops. In fact, by shrinking the
dimensions of the lines and keeping the current I constant, the current density
J gets higher and higher, increasing the line temperature as well, due to the
Joule effect.
3.2.2 Hot carriers
As MOS transistor dimensions have been scaled down faster than operat-
ing voltages, the electric field in the device has increased significantly. As a
consequence, a new parasitic phenomenon may affect the performance of the
CHAPTER 3. FAILURE ANALYSIS TECHNIQUES 13
Figure 3.2: Hot carriers generation on a NMOS transistor
MOSFETs. In particular, when the lateral electric field becomes larger than
a few MegaV/cm, carriers in the channel can gain sufficient energy (referred
to as hot carriers) to create electron-hole pairs by impact ionization on the
silicon atoms. This effect is cumulative: the carriers created can then also ac-
quire enough energy and, by further impact with the atoms, generate other
electron-hole pairs. The carriers with the most energy, larger than the SiO2
interface barrier height, and with the proper direction, will be injected into
the gate oxide.
The injected carriers may introduce interface and/or bulk oxide charges.
The consequence is degradation of the electrical parameters of the device
(mobility, threshold voltage, drain current), which is commonly called aging.
MOS physical parameters typically affected by the hot carriers phenomenon
are the density of interface states and the density of bulk oxide charges. At
transistor level the carrier mobility, the drain, the bulk currents and the ef-
fective channel length are degraded as the hot carrier injection continues. In
the Wafer Level Reliability (WLR) context, two different approaches may
be followed to investigate how sensitive a process is to the hot carriers phe-
nomenon:
ˆ Measurement of the MOSFET parameters which are directly related
CHAPTER 3. FAILURE ANALYSIS TECHNIQUES 14
to the capability of the process to generate and trap hot carriers.
ˆ An accelerated stress test performed in the most severe conditions,
then comparing the results with the characterization performed during
qualification.
In order to complete the monitoring, classic tests of longer duration should
be performed.
3.2.3 Time Dependent Dielectric Breakdown (TDDB)
TDDB is the phenomenon of oxide breakdown (or excessive leakage) due
to a high electric field being applied for a certain amount of time. Positive
charge build-up in the oxide close to the Si/SiO2 interface can cause oxide
breakdown. The source of the positive charge is the impact ionization deep
in the oxide. The consequent lowering of the energy band leads to further
electron injection which in turn leads to more hole trappings and hence a
run-away process.
The high current injected at localized spots called positive charge trap-
pings induces the Joule effect and the consequent overheating which is suffi-
cient to melt the SiO2. Prior to catastrophic oxide rupture, oxides are often
found to leak. Weak spots in the gate oxide contamination process cause ox-
ide thinning impurities and mobile ions, which in turn will end up damaging
the high stress points.
3.2.3.1 Gate Oxide Integrity
A key element in increasing transistor performance is gate oxide scaling.
As gate oxides shrink to the sub-70A˚region, the leakage mechanism changes
from Fowler-Nordheim tunneling to direct tunneling. In this case the limit-
ing factor for the operating voltages becomes gate oxide reliability. Recent