Design of Analog Integrated Circuits Robust to RF Interference

1 – Introduction
Furthermore, due to the widespread diffusion of wireless integrated systems,
which is fostered by the availability of low cost RF systems on silicon, the level of
environmental electromagnetic pollution is always increasing. As a consequence, an
always increasing level of Electromagnetic Interference (EMI) is collected by wiring
structures (cables, PCB traces, bondwires, etc...) in electronic systems from the
outside environment and it is translated into RF voltages and currents superimposed
onto SoC nominal signals. For instance, an RF incident field with a frequency of
900MHz and a peak amplitude of 10V/m, which is a common value in the proximity
of a cell phone antenna, can induce on a PCB trace of 10cm, which acts as an
electrical dipole, an RF voltage as high as 1Vpk.
Finally, the threats related to the susceptibility to RFI become more and more
severe in low voltage design. In fact, the reduction of IC power supply voltages which
is imposed by geometrical scaling and by low power constraints makes the amplitude
of RF interference very often comparable with the amplitude of ICs nominal signals
or even larger, thus strongly reducing the Signal-to-Noise Ratio (SNR) within a chip.
In conclusion, in order to be suitable to present day SoC challenges, an IC must
be designed to operate properly even in the presence of RF interference with a
magnitude comparable with nominal signals. In this work, the fulfilment of this
requirement with reference to analog ICs, which should provide accurate continuous
time, continuous amplitude waveforms, is addressed.
1.1 RFI in Analog Integrated Circuits
Analog integrated circuits, in which the information is carried by continuous time,
continuous amplitude voltage or current waveforms, have proven to be very suscep-
tible to RFI. In fact, the RF disturbances which are superimposed onto nominal
voltages and currents of an analog circuit are demodulated by the nonlinear char-
acteristics of the active devices (MOS and BJT transistors) which are included in
it, the demodulated RFI is added to the nominal output waveforms and their origi-
nal information content is corrupted [6, 7, 8]. Demodulation of RFI is particularly
hazardous because it converts out-of-band high frequency interference into in-band
low frequency interference, which cannot be separated from nominal signals through
linear filtering. In particular, in the presence of continuous wave (CW) RFI, the
output voltage of analog circuits is affected by a DC offset.
In standard analog circuits, the amount of in-band error which is due to the
demodulation of out-of-band RFI is very often much higher than the nominal level
of accuracy of these circuits. With reference to the widely employed CMOS Miller
Opamp circuit connected in the voltage follower configuration shown in Fig.1.2,
which operates from a 5V power supply, the amount of the measured RFI-induced
DC offset voltage shift is plotted in Fig.1.3 versus the peak amplitude of CW RFI
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1.1 – RFI in Analog Integrated Circuits
superimposed onto the input voltage for different RFI frequencies. It can be observed
that the RFI-induced offset voltage is comparable with the peak amplitude of CW
RFI, therefore, even for relatively small levels of RFI (e.g. 10mVpk), the RFI-induced
offset voltage is higher than the typical offset voltage due to transistor mismatch
which is usually below 1mV for this circuit topology.
In Fig.1.4 the schematic of a Kujik bandgap voltage reference, which operates
from a 5V power supply, is presented. This circuit, that is another widely em-
ployed analog building block, is designed to provide a very accurate temperature-
independent voltage reference of about 1.2V. The required accuracy of the reference
voltage over temperature is very often better than 1mV of residual thermal drift in a
temperature range between −40◦C and +120◦C, i.e. few part per million per degree.
In Fig.1.5 it can be observed how RFI can severely impair the performance of this
circuit. In particular, it can be observed that CW RFI with a frequency of 300MHz
and with a peak amplitude of about 10mV superimposed onto the power supply
voltage of this circuit is sufficient to induce an error in the output voltage that is
significatively higher than the required accuracy over temperature. Furthermore, it
can be observed that a CW RFI with a peak amplitude of about 300mV is enough
to induce a complete failure in the bandgap voltage reference operation.
The above examples show that analog integrated circuits can be particularly
susceptible to RFI and their performance in terms of accuracy can be completely
impaired by RFI with a relatively small peak amplitude. Because of the higher and
higher degree of interdependence in complex integrated systems, a failure in analog
circuit operations can induce an overall system failure which may be destructive. It
follows that conventional analog cells are not suitable to present day SoC design and
the analog IC design flow should be properly revised in order to achieve immunity
to RFI.
3
1 – Introduction
Power
Analog
Memory
I/O
I/O
RFDSP
VDD/GND
Pads
SystemonaChip
SusceptibleCircuits
EMI
RFIsources
Figure 1.1. Sources of RFI in a present-day System on a Chip (SoC) typical
architecture.
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1.1 – RFI in Analog Integrated Circuits
M1 M2
M3
vIN
GND
VDD
Vout
Figure 1.2. CMOS Miller Opamp.
0 500 1000 1500-1200
-1000
-800
-600
-400
-200
0
10 MHz
21 MHz
46 MHz
100 MHz
210 MHz
460 MHz
V [mV]RF
Dv
[mV
]
of f
Figure 1.3. CMOS Miller Opamp Susceptibility to EMI.
5
1 – Introduction
Figure 1.4. Kujik bandgap voltage reference.
Figure 1.5. Kujik bandgap voltage reference susceptibility to EMI.
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1.2 – RFI Aspects in Analog IC Design Flow
1.2 RFI Aspects in Analog IC Design Flow
The susceptibility to RFI is not considered in a standard analog IC design flow.
According to a standard design flow (Fig. 1.6a), in fact, an IC is first designed and
simulated to achieve a target performance, then it is laid out in order to reduce the
occupancy of silicon area and finally it is diffused on silicon. The aspects which are
related to the susceptibility to RFI are only considered when the chip or, more often,
the overall system in which it operates, fails either in EMI susceptibility compliance
tests or in the field. At this point, the problem could only be addressed adding
expensive external and/or on-chip shielding and filtering structures which may also
adversely affect system performance.
In the last years, EMI immunity aspects have been taken into account earlier in
the design flow by post-layout computer simulations which may predict the suscep-
tibility to EMI of a chip before it is actually integrated on silicon (Fig. 1.6b). To
this purpose, RFI-oriented models of nonlinear active devices [6, 7, 8], analog circuit
macromodels [9, 10, 11, 12, 13, 14, 15, 16, 17, 18] and parasitic extraction tools [19]
have been proposed in the literature and implemented in the last years.
These computer-aided techniques let to modify an analog IC design in the first
stages in order to enhance its immunity to EMI, nonetheless, they do not provide any
tool to design integrated circuits immune to EMI as they only provide information
on the susceptibility of a particular design and do not give insight on the origin of
the susceptibility to EMI which could be translated into design criteria to enhance
the immunity of an analog IC.
In order to face the problems related to the susceptibility to EMI of analog cir-
cuits in an effective way, a new, EMI-susceptibility aware design flow is required
(Fig. 1.6c). To this purpose, in particular, it is essential to know how the sus-
ceptibility to EMI is related to design parameters and parasitics. On the basis of
this information, it is possible to take into account the immunity to EMI as an IC
specification which can be traded off with other system requirements in the early
stage of design.
An EMI-aware analog IC design requires some analysis and design tools: to this
purpose, in particular, the behavior of analog integrated circuits in the presence
of RF interference should be predicted by an analytical model, which relates in a
simple way the susceptibility to RFI to design parameters and parasitic elements.
The insight in the operation of analog IC in the presence of RFI which can be
gained from such a model, in fact, can be exploited in order to derive design criteria
to improve the immunity to RFI of standard analog cells and to design new high-
immunity building blocks for specific analog functionalities.
7
1 – Introduction
Design
Layout
Diffusion
Immunity
Test
Production
OK
?
?
Susceptible
Design
Layout
Diffusion
Immunity
Test
Production
OK
?
?
?
Susceptible
Post-Layout
simuation
OK
?
?
?
Susceptible
EMI-aware
design
Layout
Diffusion
Immunity
Test
Production
OK
?
?
?
Susceptible
Post-Layout
simuation
OK
?
?
?
Susceptible
Figure 1.6. RFI Aspects in Analog IC Design Flows.
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1.2 – RFI Aspects in Analog IC Design Flow
This work is aimed to provide some of the tools which are required in the design
of analog integrated circuits robust to EMI. In Chapter II, in particular, the aspects
related to the nonlinear effects of RFI in analog ICs are generally considered and
the main techniques which are employed in the analysis of nonlinear electronic cir-
cuits and systems are shortly revised in order to highlight the advantages and the
drawbacks of these techniques in the investigation of the effects of EMI in analog
circuits.
In Chapter III the analytical modelling of the susceptibility to EMI of operational
amplifiers is dealt with. In particular, two Volterra series analytical models which
are suitable to predict the behavior of integrated opamp circuits in the presence
of RFI superimposed onto nominal signals and/or onto the power supply voltages
are proposed and these models are validated by experimental tests. Furthermore,
the numerical model which has been proposed by Fiori in [20] for the prediction
of the RFI-induced offset voltage in opamp circuits under large-signal excitation is
extended. In particular, a closed-form expression of the RFI-induced offset volt-
age is derived and the dependence on RFI frequency of the RFI-induced offset is
highlighted.
In Chapter IV, the analytical tools which have been proposed are employed in
order to derive design criteria to enhance the immunity to EMI of opamp circuits.
To this purpose, the influence of the feedback configuration in the susceptibility to
EMI of opamp circuits is discussed, the dependence of the intrinsic susceptibility to
EMI of IC opamps on design parameters and parasitic elements is highlighted and
the design tradeoffs which should be considered in order to enhance the immunity
to EMI are discussed. Furthermore, in Chapter IV a new opamp topology which
has been designed to achieve a high immunity to EMI is presented and its operation
principle is discussed. Moreover, the extension of the high immunity design criteria,
which have been proposed, to analog circuits and subsystems is considered.
Finally, in Chapter V, the main results which have been obtained in this research
are summarized, the topics which deserve further investigations are focused and some
concluding remarks are drawn.
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