vii
such disadvantages, Distributed Power Supply (DPS) systems with highly efficient
characteristics have been developed and widely used due to their advantages in terms of
reliability, maintainability, flexibility, and standardization. Alternative efficient power
delivering systems can be realized by using local Voltage Regulator Modules (VRM),
standing out for their low voltage and high current characteristics, which are largely
demanded by modern motherboards for computers. When the concern for the
environment and increasing energy costs call for the energy conservation, Power
Electronics is highly performing in providing applications based on fluorescent lamps
operating at high frequencies and efficiency, on motor-driven pump and on compression
systems. In particular, adjustable-speed-driven pumps and compressors have been
widely employed in process control and factory automation, due to the availability of
process computers. The increasing interest addressed to electric and hybrid vehicles
featuring reduced smog in large metropolitan areas has also led to the development in
the field of transportation of Power Electronics applications based on battery chargers.
The role of Power Electronics is aimed to satisfy the primary requirements for the
battery packs of electric and hybrid vehicles, which are high power density, high energy
density, low cost, long life, and high charging efficiency. Another important sector
where Power Electronics plays a significant role is represented by the transmission of
power over High-Voltage DC (HVDC) lines. After being converted into dc, line-
frequency voltages and currents are sent through the transmission line, where at the end
of which are newly converted in ac. Such sector shows a strong potentiality due to the
application of photovoltaic and wind-electric systems interconnected to the utility grid.
The technological advancement achieved in the field of solid-state devices has been
determinant for the progress of Power Electronics. The improvement in device
performances and the decline in cost have led several systems, such as residential,
commercial, industrial, transportation, aerospace, telecommunications and utility
systems, to use Power Electronics. Basically the power device controls the flux of
electric power from the supply to the user, with an efficiency which is strictly
depending on the electrical performances of the component. The efforts of device
designers are addressed to overcome the limits imposed by the semiconductor
technology, looking for an efficient processing of electric power. In fact, transistors
feature certain limitations which depend on the technology on which are based, hence,
viii
restricting their use to some applications. Therefore, voltage and current ratings along
with switching frequency have to meet the output requirements of the converter. To this
aim, a proper knowledge of the electrical characteristics of power devices is demanded
in order to understand the feasibility of converters and their applications, and to forecast
how the advances in semiconductor power devices can modify the converter design.
The advent of the microelectronics technology has preceded the development of
power electronics systems based on semiconductor devices. With the introduction of
power bipolar transistors in the 1950s, it was observed a constant demand to increase
the power ratings of such devices, leading to a continuous technological improvement
of the semiconductors. Although the impressive advances attained by the power
semiconductor technology, a superior attention was addressed to the microelectronics
technology, with particular emphasis on the complementary metal oxide semiconductor
(CMOS) technology, widely employed by memories and microprocessors. In 1970s, it
was recognized that the future of the power semiconductor technology was linked to the
MOS gate technology, which in respect to bipolar devices, offered ease of driving and
high switching frequency. Such characteristics allowed the widespread use of MOS
devices in different applications such as computer power supplies, telecommunications
and automotive electronics. However, bipolar devices were yet dominating in those
applications where high voltage and high current ratings were requested. In 1980s, was
concerned the approach of unify the ease of driving of the MOSFET device with the
voltage capability and low on-state conduction of the bipolar device. By this way, an
innovative structure, the Insulated Gate Bipolar Transistor (IGBT), was obtained, and
due to its rapid success, bipolar devices had soon disappeared from the market of
medium power applications. Although, many efforts have been addressed to the
obtainment of MOSFET devices based on Super Junction technology featuring both
high voltage capability and reduced on-state voltage drop. Also the approach of hybrid
structures based on bipolar and MOSFET devices was yet considered, to obtain cascode
monolithic switches to be employed in high voltage and high current applications.
By focusing on the last exposed thematic, the present thesis is intended to provide
an exhaustive analysis of innovative power devices, by means of the analytical,
experimental and simulation approach, which are applied throughout this work,
organized in the following chapters:
ix
1) Chapter one: IGBT devices submitted to short circuit conditions have been
experimentally characterized in several test conditions, in order to focus the
physical parameters which are highly involved during the fault transients. Such
a study has been also extended to multiple connections of IGBTs where current
and voltage imbalances are of concern. Besides a suitable circuit for protecting
IGBTs against fault transient has been proposed.
2) Chapter two: low voltage power MOSFETs devoted to synchronous rectifier
applications have been studied by resorting to advanced two-dimensional (2D)
finite-element grid simulations in order to explore the internal plasma dynamics
of such devices. A suitable 2D model has been implemented in the simulator,
aiming to provide a mean of investigation during design for device optimization.
Emphasis has been given to the electrical performances of the MOSFETs in
buck converters devoted to high frequency VRM applications.
3) Chapter three: high voltage Merged PiN Schottky (MPS) rectifiers based on a
Super Junction technology are analyzed by using a two-dimensional simulator in
order to explain the role of such a technology on the reverse recovery
characteristics of the diodes. A performance comparison involving the MPS
diode, a conventional PiN diode and a Schottky rectifier is proposed aiming to
highlight the level of improvement obtainable with the MPS structure device.
4) Chapter four: a new monolithic Emitter-Switching Bipolar Transistor (ESBT)
has been experimentally studied to derive a behavioral model of the device in
the PSpice simulator, by also accounting for the influence of the temperature.
The electrical performances of the ESBT have been analyzed in high voltage
power converters, particularly dwelling upon the on-state and turn-off power
dissipation losses experienced by the transistor in application.
5) Chapter five: power IGBTs in half-bridge configuration are analyzed in short
circuit condition by taking into account for the current oscillation phenomenon.
Suitable protection circuits against the fault condition occurring on IGBT
x
devices are presented and discussed. Two methods are proposed for the short
circuit protection of the high-side switch in a half-bridge configuration, which
are the sensing resistor approach and the Hall effect sensing one. Besides, an
undervoltage protection circuit devoted to rectifier systems based on IGBT
devices is proposed and analyzed.
The arguments faced in this thesis are the result of an extensive study conducted, in
a period of three years, at the University of Catania-Italy, at the University of Illinois at
Chicago, at the University of California, Irvine, and at STMicroelectronics, site of
Catania, where the experiences acquired from different researchers and professors have
been condensed in which is written in the following pages.
I wish to express my thanks to Prof. Krishna Shenai, who put me up at the
University of Illinois at Chicago, during my first year of Doctorate, at PERG
(Power Electronics Research Group) and at MSRC (MicroSystems Research
Center) labs, where I learned the use of advanced methodologies of analysis and
modeling in the field of Power Devices. I also wish to thank Prof. Keyue Smedley
for giving me the opportunity to join the Power Electronics Lab at the University
of California, Irvine, where I completed the last part of my PhD course.
1
CHAPTER I
IGBT DEVICES SUBMITTED TO FAULT CONDITIONS
I.1 INTRODUCTION
Insulated gate bipolar transistors (IGBTs) offer excellent performances in terms of
conduction characteristics and gate drive requirements, as they basically behave as BJTs
with the ease of drive of power MOSFETs. The application of IGBTs in the field of
power converters is interesting in case considerable values of currents and voltages, and
medium range switching frequency are required. Modern power applications require
IGBT devices to exhibit rugged safe operating area (SOA) and short circuit endurance,
in order to contrast critical operative conditions leading to the failure. On this subject,
device designers address a continuous effort to the improvement of the robustness
performance, within a trade-off involving conduction losses and switching frequencies.
The prediction of the stresses arising from the short circuit conditions represents a
challenging issue, among the tasks of the power converter designers, since a short
circuit can lead to the failure of the devices if suitable protection schemes are not
adopted. The protection of IGBTs against failures caused by short circuit transients is
of concern in many industrial applications and especially in the field of inverter-fed
motor drives, where the devices may be subjected to several fault types [1]. Short
circuit faults submit one or more IGBTs of the inverter to over current conditions,
which can occur at turn-on switching leading to Hard Switching Fault (HSF) transients.
Since high temperature forming in the device junction interacts with latch-up and
avalanche induced second breakdown phenomena, a regenerative mechanism, leading to
the destruction of the device, triggers. A problem associated with short circuit
transients is also the over-voltage at turn-off produced by the fall of the collector current
on the collector path stray inductance. Moreover, IGBTs submitted to a short circuit
condition during the on state conduction, namely Fault Under Load (FUL), are affected
by large current spikes which can be as far higher than the fault current in static regime.
The origin of such current spike has to be ascribed to the rapid rise of the collector
2
voltage arising from the fault. The layout parasitic and the gate driving conditions
exercise a strong influence on the fault current, thus, requiring a careful attention from
designers in order to prevent high current spikes and high power dissipations. Also the
device should be optimized in order to reduce the current spike by acting on the intrinsic
capacitances of the device, with particular reference to the gate-collector capacitance
(Miller capacitance). The FUL behavior is strictly related to the IGBT technology,
since, as previously discussed, some device parameters significantly manifest their
influence on the current spike.
I.2 HARD SWITCHING FAULT ON IGBT DEVICES
During short circuit transients, an IGBT carries a current up to 4÷5 times greater than
its rated value, while its voltage is close to the bus voltage, thus giving rise to
unsustainable power losses. In these conditions, significant self-heating occurs,
eventually leading to thermal breakdown of the device [2]. Moreover, the presence of
the parasitic transistor can also affect the ruggedness of the IGBT [3]. A half cross-
section of an IGBT is shown in Fig. 1.1, where its equivalent electric, which is made up
by a MOSFET and a PNP bipolar transistor, is superimposed. Also shown is the
parasitic NPN transistor responsible together with the PNP for undesired eventual latch-
up of the device. In short-circuit conditions, as long as the device conducts current for a
longer time than its permissible short-circuit time, the temperature increase leads to a
high impact-generation rate, while the reverse biased PN base-drift junction sustains a
large electric field. This produces an increase of carrier generation, and accounting for
the high temperature, regenerative process initiates leading to a thermally assisted
carrier-multiplication and finally to the breakdown of the device.
The robustness of power devices is an essential requisite for their use in applications
like inverter-fed motor drives, where high levels of stressing energies frequently occur.
In this section, HSF conditions, which the device of a leg may experience, are analyzed
and discussed. In this fault condition the inductive load of Fig. 1.2 is previously short-
circuited, by turning on the auxiliary switch, and then the device under test is turned on
directly into the fault.
3
Fig. 1.1. Equivalent electric circuit superimposed on a half cross-section of an IGBT device.
Accordingly, the IGBT instantaneously withstands all the bus voltage and the fault
current is only limited by the gain of the device. This causes high power and energy
losses, leading to one of the two failure mechanisms above-mentioned. In order to
avoid this catastrophic evolution, thus reaching again safe condition, the IGBT must be
turned off within the short-circuit withstanding time through a dedicated protection
circuit. In this case study, the device under test is supplied at 300 V dc bus and a
maximum short circuit operation time of 10 µs is allowed without device failure.
Fig. 1.2. Test circuit prepared to do the laboratory experiments in HSF conditions with a single switch.
The tested devices are Punch-Through IGBTs (PT-IGBT), having 600 V breakdown
voltage and 20 A nominal current, with improved short circuit ruggedness. The devices
belong to the last IGBT generation which are manufactured in the mesh overlay
technology, i.e. a strip-based concept realized from a P -doped mesh structure (the
4
body of IGBT) where
+
N -doped strips, which are directly diffused and representing
the emitter of the IGBT, change the more traditional approach with cells [4]. A three-
dimensional representation of the described IGBT is shown in Fig. 1.3.a). This new
technological solution allows to manufacture IGBTs with a reduced on-state voltage
drop, which is obtained thanks to a decrease of the on-state resistance (till to 20% of
reduction). The presence of a deep body
+
P -layer makes the device free from the
static latch-up problem. The short circuit ruggedness has been improved with the
technique of ballast resistance. Two strip sections, together with an overview and the
equivalent electrical circuit of the manufactured device are shown in Figs. 1.3.b) and
1.3.c), respectively. The extension of the
+
P -layer over the metallic contact increases
the path of the electron current from the MOSFET source to the cathode, thus creating a
ballast resistance
b
R , as it is shown in the equivalent circuit of Fig. 1.3.c). In short
circuit conditions the increase of the voltage
b
V , across the ballast resistance, leads to a
negative feedback on the gate-source voltage of the intrinsic MOSFET, consequently
reducing its drain current. In turns, that means the limitation of the IGBT collector
current.
Fig. 1.3. IGBT with mesh layout: a) three-axis view of the device structure, b) details on the strip layout,
c) equivalent electrical circuit with the ballast resistance.
The electrical parameters that mainly influence the current behavior are related to the
driving circuit. In particular, the gate voltage magnitude determines the collector
5
current, which increases consequently to an increase of the former. This consideration
results evident in Fig. 1.4, where three different short circuit conditions are shown in
case of three different values of the gate voltage
GE
V , thus leading to three different
values of the collector current
C
I
during the tests.
A direct correlation between the two quantities clearly appears, so it is immediate to
conclude that a useful action to perform is the intervention on the gate voltage (i.e. the
voltage reduction by means of clamping diodes on the gate side). In fact, the gate
voltage influences the short circuit resistance time of the device since the higher is the
collector current the higher will be the power dissipation. Hence, a dynamic reduction
of the gate voltage during the fault increases the robustness of the device being a
conducting time longer than 10 µs permissible.
Fig. 1.4. Hard switching fault at several gate voltage amplitudes and Tj=125 °C with R
G
=100 Ω and
V
CE
=300 V. V
GE
=10 V/div; I
C
=20 A/div; t=2 µs/div.
Another problem consequent to the short-circuit conditions is the considerable
voltage spike at turn-off (see Fig. 1.5), due to both the high rate of change of the
collector current and to the collector-path stray inductance [5, 6]. Since the fall time of
the current is directly dependent on the input time constant
ISSG
CRτ = of the IGBT,
where
G
R is the gate resistor, a high τ is needed to reduce the transient voltage peak.
This can be realized by means of an increase of
G
R or
ISS
C .
In order to promote a suitable protective action against a short circuit, it’s necessary to
identify the electrical parameters on which acting to accomplish safe short circuit
operation of IGBTs and implement the corrective actions. These are the major
6
guidelines that have been pursued in proposing, analyzing and designing the short
circuit protection circuit, but other minor functions have been implemented, too.
Fig. 1.5. Hard switching fault at Tj =125 °C with R
G
=10 Ω, V
GE
changing from –5 V to 15 V and again
–5 V. V
GE
=20 V/div; V
CE
=100 V/div; I
C
=50 A/div; t=2 µs/div.
As long as a HSF condition is imposed to IGBTs, the problem of the high power
dissipation, due to the occurrence of both high current and high voltage, can be faced by
means of an approach of limiting the fault current, followed by the safe turn-off of the
device. By an extended characterization of the device, which has been carried out
through short circuit tests on 600V-20A punch-through IGBTs, in case of HSF transient
conditions, the correlation between the short circuit withstanding time and the current
peak, as function of the gate voltage, has been determined and the results are shown in
Fig. 1.6.
Fig. 1.6. Short-circuit withstanding time and current peak vs. the gate voltage.
The approach of limiting the gate voltage may be realized by means of the circuit
depicted in Fig. 1.7.a), where a sensing diode, implementing the voltage desaturation
method [7], enables the clamping and the safe turn-off circuit when a fault occurs. As
7
the IGBT device is gated on in a HSF condition, the clamping circuit switches on the
transistor
1
Q , thereby reducing the gate voltage to a value opportunely lower than 15 V
(which is fixed by the Zener diode Z ) [8]. This serves to decrease the fault current as it
is shown in Fig. 1.7.b), where the tests with three different threshold values of the
clamping voltage are reported. It is worth noting that small differences among these
voltage values lead to significant differences among the relative fault currents, thus
allowing the on-state time of IGBT in fault condition to be matched according to a
trade-off derived from the data of Fig. 1.6.
Based on the curves of Fig. 1.7.b), the power converter designers can arrange a
protection with a suitable trade off between the intervention time and over current
figures. As a consequence, the device can hold these conditions as long as 10 µs,
without approaching the failure. Nevertheless, a safe turn-off it is also necessary, since
a)
b)
Fig. 1.7. a) Protection circuit performing the gate voltage clamping and the safe turn-off, b) Voltage and
current waveforms relative to a HSF transient with the intervention of the protection circuit. V
IN
=18 V,
V
GE
=10 V/div, I
C
=50 A/div, t=5 µs/div.
8
the current magnitude is beyond the rating of the device and moreover it sustains all the
bus voltage. To this aim, the transistor
2
Q is switched on after a settable delay time,
which depends on the current level, and it allows the safe turn off operation.
I.3 FAULT UNDER LOAD ON IGBT DEVICES
The FUL behavior is by definition the short circuit transient occurring while the
device is in its on-state condition. The test circuit depicted in Fig. 1.8.a) allows
simulating the operative condition of an actual undesired transient, which causes the
short circuit of the load during the normal loaded conditions. This fault submits the
collector to a voltage transient while the device is conducting and the gate-emitter
voltage is high cause the collector-gate current injected through the Miller capacitance
to the gate side. The current increases from the initial value and experiences a short
circuit transient of the current. Exhausted this one, since the collector voltage reaches
the bus voltage, the collector current settles to the static regime value corresponding to
the on-state gate-emitter voltage of 15 V. The qualitative waveforms during the FUL
condition are reported in Fig. 1.8.b). The influence of some electrical parameters
involved with the transient behavior have been highlighted in such a figure. The IGBT
parasitic capacitance has the playing role in determining the amplitude of the gate
voltage and as a consequence of the collector current peak.
R
G1
T
AUX
T
1
L
C
Driver
Driver
AUX
t
V
G
0
V
G_AUX
0
t
V
G
V
G_AUX
a)
t
V
CE
L
s
I
C
t
0
t
GE
V
Ci=f(CGD ,CGS)
0
0
Ic,peak
V
DC
b)
Fig. 1.8. a) Electrical circuit of the laboratory workbench, and timing of the gate driving signals and b)
traces depicting in principle the FUL operative conditions.
9
The collector path stray inductance dictates the fault current rise slope during the
collector voltage increase and the collector voltage spike at turn-off. The fast rise of the
collector voltage,
CE
V , which is due to the high dV/dt, leads to a sudden voltage
increase on the gate-emitter voltage,
GE
V , through the parasitic capacitance
i
C , which
is function of the gate-emitter capacitance,
GE
C , and of the gate-collector capacitance,
GC
C
.
The short circuit current shows a peak due to the increase of the gate voltage, and
this peak value is strictly related to both the rise time of the collector voltage and the
layout parasitic inductance. The current peak
peakC,
I
is approximately given by [9]:
rise
s
DC
peak
C,
t
L
V
I ⋅=
(1.1)
where
DC
V is the dc link voltage,
s
L is the parasitic inductance of collector-emitter
path and
rise
t
is the rise time of the collector voltage. Finally, the voltage peaks (rising
and falling edges) are strictly related to the layout parasitic inductances as well as to the
current fall time as given by the following relation:
fall
maxC,
sDCpeakCE,
t
I
LVV ⋅+=
(1.2)
where the current
maxC,
I
is the permanent short circuit current value.
The experimental short circuit tests in FUL conditions have been carried out at
GE
V =15 V and
CE
V =300 V. However, as discussed in the next sections, the gate-
emitter voltage attains higher values and the current temperature coefficient is observed
to change sign during the FUL transient. Indeed, depending on the level reached by the
collector current, a temperature increase may lead to a current increase or decrease.
Also the temperature plays an important role on both the static and dynamic fault
current. The static characteristics of IGBTs change as function of the temperature
variation. The analysis of such variations due to the thermal behavior is also important
in order to understand the features of the device in short circuit conditions. IGBTs
show a singular variation of some internal quantities as function of the temperature.
Consequently, with reference to the collector current
C
I
versus the collector-emitter
10
voltage
CE
V , the temperature coefficient of the device current has a sign which is
dependent on the prevalence of the MOSFET contribution or the bipolar one. As an
example, the static curve with
GE
V =17 V has been determined at two different junction
temperatures (namely
j
T =25 °C, and
j
T =125 °C) and the results are shown in Fig.
1.9.a), where the cross point of the characteristics has been pointed out, thus showing
the change of the temperature coefficient from positive to negative value.
If the device is let to operate at
GE
V =15 V, prescinding from the collector voltage
value, a positive temperature coefficient, as reported in Fig. 1.9.b), is to be expected.
That means the trace of the collector current at 125 °C is higher than the one at 25 °C.
When the gate- emitter increases over the designed value, the inversion of the
temperature coefficient occurs, leading to a reduction of the current level [10].
a)
b)
Fig. 1.9. Traces of the static characteristics at two different junction temperatures showing the negative
and positive values of the temperature coefficient: a) V
GE
=17 V, b) V
GE
=15 V.
The experimental tests have been carried out in several operative conditions by
means of the laboratory circuit reported in Fig. 1.8.a).
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